REPORT SCOPE
INTRODUCTION
ASICs (application-specific integrated circuits) with attractive NRE (non-recurring engineering) metrics are the proverbial holy-grail of semiconductor manufacturing. ASICs have been around for a long time and have survived the notoriety of being resource burners. As a matter of fact, the ASIC sector has maintained steady growth, often outpacing the overall semiconductor industry. This report is an attempt to unravel the reasons that make ASICs such a resilient design methodology, and to examine and forecast the current and future global market for ASICs.
An interesting dimension to the ASIC industry is the development and hype surrounding the introduction of structured ASICs. This study forecasts that while structured ASICs read all right on paper, their market performance is does not deliver justice to the high expectations that it has set for itself.
Finally, ASIC prospects cannot be fully appreciated unless the implications of FPGAs, its principal competitor, are factored into the analysis. Although originating from totally different design philosophies, ASICs and field programmable gate arrays (FPGAs) continue to carry their competitive battle to new and high-end applications.
STUDY GOALS AND OBJECTIVES
This study has the following goals and objectives:
- Forecasting the market size for ASICs
- Breaking down the ASIC market into structured and non-structured ASICs
- Classifying the structured and non-structured ASIC markets on regional, as well as on an end-application category basis.
- Breaking down the end-application categories along specific device use cases and in turn breaking these use cases along structured and non-structured ASICs.
- Breaking down end-application categories along geographic regions
- Analysing the impact and prospects of and for FPGAs vis-à-vis ASICs in all individual end-application categories
- Providing an overview of various ASIC design methodologies
- Explaining the ASIC stakeholder value chain
- Summarizing the ASIC related initiatives of key stakeholders
- Analyzing mainstream ASIC patents
REASONS FOR DOING THE STUDY
While ASICs are a fairly well-established methodology of synthesizing integrated circuits (ICs), they are facing increasingly severe threats in the form of programmable methodologies such as FPGAs. While the ASIC industry has responded with the development of structured ASICs, the market response to this initiative has been less than encouraging. In this context, the report places the following aspects into perspective:
- Strengths and weaknesses of ASICs
- Prospects for ASICs across application categories, end-user devices, and geographic regions
- How will structured ASICs perform in the next 5 years
- Competitive scenario for ASICs in each application category
SCOPE OF THE REPORT
The report forecasts the size of the structured and non-structured ASIC market between 2009 and 2014.
The executive summary provides a snapshot of key findings of the report.
The section on technology and applications overview covers the technical aspects of conventional as well as structured ASIC design and fabrication methodologies with an emphasis on how structured ASICs plug the gaps in ASIC functionalities. It covers history of ASICs and describes ASIC types such as gate-array, full-custom, standard-cell, embedded, hybrid and structured ASICs, and concludes by discussing the drivers and challenges for ASICs.
The section on market breakdown by applications provides a granular analysis of ASIC usage in multiple use cases in leading application categories. Apart from providing a regional analysis of ASIC usage in application end categories, this section provides a detailed implication for and of competing methodologies.
The section on stakeholders explains the criterion for classification of stakeholders – ASIC user companies, foundries, electronic design automation (EDA) suppliers, IP owners, semiconductor specialists, and ASIC specialists. It also provides the lowdown on the ASIC related initiatives of key companies in each category.
The U.S. Patent Analysis section highlights the patenting activity underway in the area of ASICs. The section classifies the patents awarded according to their position in the ASIC value chain. It also provides a geographic and distribution by company of ASIC patents.
The report is punctuated with numerical findings and projections that substantiate and drive the theoretical discussion.
INTENDED AUDIENCE
The report will be relevant to the following stakeholders:
- Original equipment manufacturers (OEMs) and original design manufacturers (ODMs) by providing an analysis of the strengths and weaknesses of ASICs vis-à-vis other design methodologies and by categorizing ASICs into structured and several non-structured categories
- Semiconductor specialists in understanding the intellectual property (IP) and non-recurrent engineering (NRE) implications of employing ASICs
- Niche and established ASIC suppliers by providing a detailed forecast of the ASIC market
- IP owners by identifying the nature and contribution of key design blocks in ASICs
METHODOLOGY AND INFORMATION SOURCES
Both primary and secondary research methodologies were used in this study. Industry experts were interviewed; secondary sources included industry consortia, individual company financial statements, published opinions, and other published sources.
ABOUT THE AUTHOR
Kaustubha Parkhi has worked in a broad range of functional roles with leading telecom operators and service providers such as Reliance Infocomm, Ramco Systems, and BPL Cellular. He has written on a wide-ranging array of telecommunications and electronics-related subjects based on his critical analysis of the underlying technology and its business impact. Kaustubha holds a B.S degree in Electronics and Telecommunications and a M.B.A. degree in Systems.
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DISCLAIMER
The information developed in this report is intended to be as reliable as possible at the time of publication and of a professional nature. This information does not constitute managerial, legal, or accounting advice; nor should it serve as a corporate policy guide, laboratory manual, or an endorsement of any product, as much of the information is speculative in nature. The author assumes no responsibility for any loss or damage that might result from reliance on the reported information or its use.
