Wafer-level Packaging: Technologies and Global Markets
The global wafer-level packaging (WLP) market was valued at $1.3 billion in 2013. This market is expected to grow from $1.6 billion in 2014 to $4.9 billion by 2019, with a compound annual growth rate (CAGR) of 24.5% from 2014 to 2019.
- An overview of the global markets and technologies for wafer-level packaging.
- Analyses of global market trends, with data from 2013 and 2014, and projections of CAGRs through 2019.
- Coverage of technologies including: Flip-Chip, 3-D WLP, Conventional CSP, Wafer Level CSP, Compliant WLP, Nano WLP, and others.
- Information on integration techniques including Fan-out WLP, Fan-in WLP, TSV, IPD.
- Details concerning applications, including consumer electronics, automotive, industrial, defense and aerospace, medical, and others.
- A regional analysis: North America, Europe, Asia-Pacific, and RoW.
- An industry and competitive analysis.
- A relevant patent analysis.
- Profiles of major players in the industry.
The scope of the study includes the present and upcoming market trends of WLP, including which mode of integration is most commonly used.
The report covers the WLP market by the following categories and segments:
- Technology: Flip chip, 3-D WLP, conventional chip-scale package (CSP), wafer-level CSP, compliant WLP, Nano-WLP and others.
- Integration: Fan-out WLP, Fan-in WLP, Through Silicon Via (TSV), Integrated Passive Device (IPD).
- Applications: Consumer electronics, automotive, industrial, defense and aerospace, medical, others.
- Region: North America; Europe; Asia-Pacific and ROW.
- Industry and competitive analysis.
- Patent analysis.
- Company profiles.
Sinha G. Gaurav focuses on electronics and semiconductors markets, robotics and nanotechnology. His publications range from factory automation and big data to industrial controls and helmet-mounted displays. He holds a bachelor's degree in electrical engineering from Rajasthan University and an MBA degree in finance from ICFAI Business School.